0hmX/am3352

scripts/diagnose-ddr-d14-transition.ts

/** One existing single-turn CPU-prefix template, before any RAM escape change. */
import{readFileSync,writeFileSync,mkdirSync}from'node:fs'
import{resolve}from'node:path'
import{createHash}from'node:crypto'
import{verifyDdrSystemCopper}from'./check-ddr-system-copper'
import{planDdrGroundAntipads}from'./ddr-ground-plane-antipads'
import{classifyHostFixedContact}from'./audit-ddr-host-fixed-contacts'
const [dir,out]=process.argv.slice(2),read=(p:string)=>JSON.parse(readFileSync(resolve(dir,p),'utf8')),hash=(x:any)=>createHash('sha256').update(JSON.stringify(x)).digest('hex'),c=read('candidate.circuit.json'),h=read('host-bundle.json'),i=read('routing-input.json'),r=read('report.json'),connection=i.connections.find((c:any)=>c.source_trace_id==='source_trace_692')
if(hash(c)!==r.candidateCircuitSha256||hash(h.traces)!==r.hostTracesSha256||!connection)throw Error('Current board differs')
const cpu=connection.pointsToConnect.find((p:any)=>p.x>0),via={x:2.48,y:.8},collar={x:cpu.x-.2,y:cpu.y},m=Math.min(collar.x-via.x,via.y-collar.y),corner={x:collar.x-m,y:collar.y+m},trace={type:'pcb_trace',pcb_trace_id:'planned_D14_inner6_transition',source_trace_id:connection.source_trace_id,connection_name:connection.name,route:[cpu,collar,corner,via].map(p=>({route_type:'wire',x:p.x,y:p.y,layer:cpu.layer,width:.12})).concat([{route_type:'via',...via,from_layer:cpu.layer,to_layer:'inner6',via_diameter:.4572,via_hole_diameter:.254},{route_type:'wire',...via,layer:'inner6',width:.12}] as any)},ids=new Set(h.traces.map((t:any)=>t.pcb_trace_id)),fixed=c.filter((e:any)=>!ids.has(e.pcb_trace_id)&&e.type!=='pcb_copper_pour'),conductor=verifyDdrSystemCopper(fixed,[...h.traces,trace],i.connections,{},50,{reportSameNetContacts:true})
let planes:any,physical:any;if(!conductor.errors.length&&!conductor.violations.length){planes=planDdrGroundAntipads(c.filter((e:any)=>e.type==='pcb_copper_pour'),[{...via,net:'DDR_D14'}]);physical=verifyDdrSystemCopper([...fixed,...planes.planes],[...h.traces,trace],i.connections,{},50,{reportSameNetContacts:true})}
const contacts=(physical?.sameNetContacts??conductor.sameNetContacts??[]).filter((x:any)=>x.aShape.traceId===trace.pcb_trace_id||x.bShape.traceId===trace.pcb_trace_id).map((x:any)=>classifyHostFixedContact(x,trace)),check=physical??conductor,accepted=!!physical&&!check.errors.length&&!check.violations.length&&check.angles.valid&&!check.joinedBends.length&&contacts.length===1&&contacts[0].classification!=='unintended-interior-contact'&&(()=>{const endpoint=c.find((e:any)=>e.pcb_breakout_point_id===cpu.pointId),saved=fixed.find((e:any)=>e.type==='pcb_trace'&&e.pcb_trace_id===contacts[0].fixedTraceId),same=(p:any)=>p.layer===cpu.layer&&Math.hypot(p.x-cpu.x,p.y-cpu.y)<1e-7;return saved?.source_trace_id===endpoint?.source_trace_id&&same(saved.route.at(-1))&&[contacts[0].hostShape.a,contacts[0].hostShape.b].some(same)&&[contacts[0].fixedShape.a,contacts[0].fixedShape.b].some(same)})()
mkdirSync(out,{recursive:true});writeFileSync(resolve(out,'report.json'),JSON.stringify({accepted,sourceParent:resolve(dir),parentCandidateSha256:hash(c),captureHash:r.captureHash,trace,conductor,physical,contacts,scope:'Partial CPU transition only. Existing RAM D14 remains inner4; a separately validated retained-via RAMinner6 escape and host are required. No complete D14 or electrical qualification.'},null,2));if(planes)writeFileSync(resolve(out,'planes.json'),JSON.stringify(planes.planes,null,2));console.log(JSON.stringify({accepted,errors:check.errors.length,violations:check.violations.length,first:check.violations.slice(0,3)}))