0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

scripts/render-ddr-system-progress.ts

import {readFileSync,writeFileSync} from 'node:fs'
import {resolve} from 'node:path'
import {Resvg} from '@resvg/resvg-js'
import {convertCircuitJsonToPcbSvg} from 'circuit-to-svg'
import {verifyDdrCapture} from './ddr-capture-provenance'
const [dir,candidateDir]=process.argv.slice(2)
if(!dir||!candidateDir)throw Error('Usage: capture-dir normalized-candidate-dir')
const read=(p:string)=>JSON.parse(readFileSync(p,'utf8'))
const {captureHash,snapshot}=verifyDdrCapture(dir),candidate=read(resolve(candidateDir,'candidate.physical.json')),report=read(resolve(candidateDir,'physical-report.json'))
if(candidate.captureHash!==captureHash||report.captureHash!==captureHash||candidate.layerSpace!=='physical')throw Error('Mismatched capture')
const json=[...read(resolve(dir,'unrouted.circuit.json')),...(snapshot.hostProfiles?[]:read(resolve(dir,'corridor-leads.json'))),...candidate.traces]
const count=report.connectivity.filter((c:any)=>c.connected).length
const panels=['top','inner2','inner4','inner6'].map((layer,i)=>{
 const svg=convertCircuitJsonToPcbSvg(json,{layer:layer as any,width:1100,height:800,viewport:{minX:-21,maxX:23,minY:-17,maxY:17},shouldDrawRatsNest:false})
 return `<text x="${20+(i%2)*740}" y="${150+Math.floor(i/2)*600}" fill="white" font-size="22">${layer}</text>`+svg.replace('<svg ',`<svg viewBox="0 0 1100 800" x="${20+(i%2)*740}" y="${160+Math.floor(i/2)*600}" `).replace('width="1100"','width="720"').replace('height="800"','height="524"')
})
const svg=`<svg xmlns="http://www.w3.org/2000/svg" width="1500" height="1330"><rect width="1500" height="1330" fill="#10151c"/><g font-family="sans-serif"><text x="24" y="42" fill="white" font-size="30">AM3352 + two MT41K512M8 — partial host copper</text><text x="24" y="80" fill="#ffd173" font-size="23">${count}/50 nets connected · geometry checked · DDR timing and power unfinished</text><text x="24" y="112" fill="#abc0d0" font-size="18">CPU at right, RAMs at left. Includes saved fanouts and checked host routes. This is not a fabrication-ready board.</text>${panels.join('')}</g></svg>`
writeFileSync(resolve(candidateDir,'progress.svg'),svg);writeFileSync(resolve(candidateDir,'progress.png'),new Resvg(svg).render().asPng())
console.log(resolve(candidateDir,'progress.png'))