0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version: 1.0.5
License: unset
Stars: 0

src/ddr-memory-support.ts

import type { DdrMemoryPin } from './ddr-memory'

/** Micron 4Gb DDR3L Rev R, ball descriptions p20, output calibration p67.
 * https://atta.szlcsc.com/upload/public/pdf/source/20241017/DD693FFA66FA4C721D9CFF3534518DFE.pdf
 * This is a wiring contract; it does not place capacitors or synthesize a PDN.
 */
export const MT41K512M8_SUPPORT = {
  part: 'MT41K512M8DA-107 IT:P',
  voltageForAM3352: 1.5,
  referenceRatio: 0.5,
  zqResistanceOhms: 240,
  zqTolerancePercent: 1,
  zqReturn: 'VSSQ',
  tdqsEnabled: false,
} as const

export interface DdrMemorySupportTargets {
  vdd: string
  vddq: string
  ground: string
  vrefca: string
  vrefdq: string
  /** Selector of the RAM-specific 240-ohm resistor's signal pad, NOT ground. */
  zqResistor: string
}

/** Preserve every physical supply ball, avoiding the dangerous practice of
 * connecting one representative VDD/VSS ball and leaving others floating.
 * VREF is a quiet half-rail input. ZQ needs a separate resistor per memory IC.
 */
export function getDdrMemorySupportConnections(pins: readonly DdrMemoryPin[], targets: DdrMemorySupportTargets): Record<string,string> {
  for (const [name,target] of Object.entries(targets)) if (!target.trim()) throw Error(`Missing RAM support target ${name}`)
  if ([targets.ground, targets.vdd, targets.vddq, targets.vrefca, targets.vrefdq].includes(targets.zqResistor)) throw Error('ZQ must connect through its own 240-ohm resistor')
  const result: Record<string,string> = {}
  const used=new Set<string>()
  for (const pin of pins.filter(p=>p.routed)) {
    if (used.has(pin.terminal)) throw Error(`Duplicate RAM terminal ${pin.terminal}`)
    used.add(pin.terminal)
    if (/^VDDQ_/.test(pin.terminal)) result[pin.terminal]=targets.vddq
    else if (/^VDD_/.test(pin.terminal)) result[pin.terminal]=targets.vdd
    else if (/^VSS(?:Q)?_/.test(pin.terminal)) result[pin.terminal]=targets.ground
    else if (pin.terminal==='VREFCA') result[pin.terminal]=targets.vrefca
    else if (pin.terminal==='VREFDQ') result[pin.terminal]=targets.vrefdq
    else if (pin.terminal==='ZQ') result[pin.terminal]=targets.zqResistor
  }
  for (const terminal of ['VREFCA','VREFDQ','ZQ']) if (!result[terminal]) throw Error(`Missing required RAM terminal ${terminal}`)
  for (const prefix of ['VDD_','VDDQ_','VSS_','VSSQ_']) if (!Object.keys(result).some(t=>t.startsWith(prefix))) throw Error(`Missing RAM supply family ${prefix}`)
  return result
}

src/ddr-memory-support.ts

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