0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

tests/ddr-all-trace-junctions.test.ts

import{test,expect}from'bun:test'
import{auditDdrTraceJunctions,verifyDdrSystemCopper}from'../scripts/check-ddr-system-copper'
const wire=(x:number,y:number,layer='inner1')=>({route_type:'wire',x,y,layer,width:.12})
const trace=(id:string,route:any[],net='s')=>({type:'pcb_trace',pcb_trace_id:id,source_trace_id:net,route})
const source={type:'source_trace',source_trace_id:'s',connected_source_port_ids:[]}
test('old-only90degree corner is caught without applying fresh-signal layer gate',()=>{
 const circuit=[source,trace('a',[wire(-1,0),wire(0,0)]),trace('b',[wire(0,0),wire(0,1)])]
 expect(verifyDdrSystemCopper(circuit,[],[],{},0).joinedBends).toEqual([])
 const all=auditDdrTraceJunctions(circuit);expect(all.errors).toEqual([]);expect(all.valid).toBe(false);expect(all.joinedBends).toHaveLength(1);expect(all.joinedBends[0]).toMatchObject({layer:'inner1',degree:2})
})
test('all-only interior T and X crossings are caught while valid Y branch remains legal',()=>{
 const t=[source,trace('a',[wire(-1,0),wire(1,0)]),trace('b',[wire(0,0),wire(0,1)])]
 expect(auditDdrTraceJunctions(t).joinedBends[0]?.degree).toBe(3)
 const x=[source,trace('a',[wire(-1,0),wire(1,0)]),trace('b',[wire(0,-1),wire(0,1)])]
 expect(auditDdrTraceJunctions(x).joinedBends[0]?.degree).toBe(4)
 const y=[source,trace('a',[wire(-1,0),wire(0,0)]),trace('b',[wire(0,0),wire(1,1)]),trace('c',[wire(0,0),wire(1,-1)])]
 expect(auditDdrTraceJunctions(y).valid).toBe(true)
})
test('exact same-net via terminates fixed planar run; nearby or foreign via does not',()=>{
 const c=[source,trace('a',[wire(-1,0),wire(0,0)]),trace('b',[wire(0,0),wire(0,1)])],via={type:'pcb_via',pcb_via_id:'v',source_trace_id:'s',x:0,y:0,outer_diameter:.4572,hole_diameter:.254,layers:['top','inner1','bottom']}
 expect(auditDdrTraceJunctions([...c,via]).valid).toBe(true)
 expect(auditDdrTraceJunctions([...c,{...via,x:.01}]).valid).toBe(false)
 expect(auditDdrTraceJunctions([...c,{...via,source_trace_id:'foreign'}]).valid).toBe(false)
})