0hmX/am3352

tests/ddr-board-rules.test.ts

import { expect, test } from 'bun:test'
import { AM3352_BALL_MAP } from '../src/pin-map'
import { ddrNetClass } from '../src/ddr'
import { auditDdrBoard, DDR_EVIDENCE_GATES, type DdrBoardMeasurements } from '../src/ddr-board-rules'

// Deliberately synthetic measurements: verify evaluator boundaries, not hardware.
function synthetic(): DdrBoardMeasurements {
  return {
    clockMHz: 400, cpuOrderingCode: 'synthetic-test-only',
    memoryPart: 'MT41K512M8DA-107 IT:P', memoryCount: 2, topology: 'two-x8-same-side', caclmMm: 30, dqlmMm: [30, 40],
    routes: Object.values(AM3352_BALL_MAP).filter(n => ddrNetClass(n)).map(signal => {
      const cls = ddrNetClass(signal)!
      return { signal, connectedMemoryBytes: cls.endsWith('0') ? [0] : cls.endsWith('1') ? [1] : [0, 1],
        fullLengthMm: cls.endsWith('1') ? 40 : 30, minimumWidthMm: .1016, maxTurnDegrees: 45, reducedSpacingLengthMm: 0,
        ...(['CK', 'ADDR_CTRL'].includes(cls) ? { addressSegments: { a1a2Mm: 25, a3Mm: 5, asMm: [1, 1], atMm: 1 } } : {}),
      }
    }),
  }
}
test('complete geometric measurements cannot pass without board evidence', () => {
  const result = auditDdrBoard(synthetic())
  expect(result.failures).toEqual([])
  expect(result.measuredRulesPass).toBe(true)
  expect(result.acceptanceEvidenceComplete).toBe(false)
  expect(result.gates.every(g => g.status === 'unverified')).toBe(true)
})
test('empty interface and missing address segmentation fail closed', () => {
  expect(auditDdrBoard({ routes: [] }).measuredRulesPass).toBe(false)
  const input = synthetic()
  delete input.routes.find(r => r.signal === 'DDR_CK')!.addressSegments
  expect(auditDdrBoard(input).failures.some(f => f.code === 'address-segments')).toBe(true)
})
test('detects host skew, wrong byte destination, sharp turn and spacing budget overflow', () => {
  const input = synthetic(), route = input.routes.find(r => r.signal === 'DDR_D0')!
  route.fullLengthMm += .636
  route.connectedMemoryBytes = [1]
  route.maxTurnDegrees = 90
  route.reducedSpacingLengthMm = 31.751
  const codes = auditDdrBoard(input).failures.map(f => f.code)
  for (const code of ['byte-0-dq-skew', 'destinations', 'bend', 'reduced-spacing-budget']) expect(codes).toContain(code)
})
test('malformed measurements cannot bypass comparisons with NaN', () => {
  const input = synthetic()
  input.routes[0]!.fullLengthMm = NaN
  input.routes[0]!.minimumWidthMm = NaN
  expect(auditDdrBoard(input).measuredRulesPass).toBe(false)
})
test('evidence needs artifact provenance and cannot hide measured failure', () => {
  const input = synthetic()
  input.evidence = Object.fromEntries(DDR_EVIDENCE_GATES.map(g => [g, { status: 'pass', artifact: 'synthetic-test-report' }]))
  expect(auditDdrBoard(input).acceptanceEvidenceComplete).toBe(true)
  input.evidence.fabricatorImpedance = { status: 'pass', artifact: '' }
  expect(auditDdrBoard(input).acceptanceEvidenceComplete).toBe(false)
  input.routes[0]!.maxTurnDegrees = 90
  expect(auditDdrBoard(input).acceptanceEvidenceComplete).toBe(false)
})

test('matched but overlong bytes fail nominal length independently of skew', () => {
  const input = synthetic()
  for (const route of input.routes) if (['DQ0', 'DQS0'].includes(ddrNetClass(route.signal) ?? '')) route.fullLengthMm += 1
  const result = auditDdrBoard(input)
  expect(result.failures.some(f => f.code === 'byte-0-nominal-length')).toBe(true)
  expect(result.failures.some(f => f.code.includes('skew'))).toBe(false)
  delete input.dqlmMm
  expect(auditDdrBoard(input).failures.some(f => f.code === 'byte-0-dqlm')).toBe(true)
})