AnasSarkiz/ble-pedometer

This code defines and configures various electronic hardware components such as surface-mount resistors, crystals, diodes, transistors, connectors, and switches with their physical footprints, schematic symbols, and 3D CAD models for PCB assembly.

Version
1.0.7
License
unset
Stars
0

PACKAGE_UPDATE_REPORT.md

# Export integration audit — 2026-09-06

The released exporter fixes are integrated using the official public APIs. The user authorized publication of this engineering-review revision on 2026-09-06. This is not a manufacturing release.

## Current dependencies and workflow

- tscircuit 0.0.2464, circuit-json 0.0.485, circuit-to-svg 0.0.413.
- Direct, exact exporter dependencies: circuit-json-to-gerber 0.0.104, circuit-json-to-bom-csv 0.0.17, circuit-json-to-pnp-csv 0.0.13.
- `bun run export:manufacturing-review` renders the unchanged board through the public core API, validates physical geometry and exported drill spans, and checks the complete fitted inventory before writing review files.
- The BOM library's documented resolver reads package descriptions from `assembly-parts.ts` and rejects unexpected MPN/supplier pairs. The released exporters themselves exclude DNP parts and bare test pads; no generated CSV or Circuit JSON is patched.
- The old CLI-bundled `tsci export -f gerbers` still uses obsolete exporters and must not be used for this board.

## Current validation

- TypeScript, frozen-lockfile install and `git diff --check`: pass.
- 28 tests, 4 snapshots, 1137 assertions: pass. New regressions cover physical drill precedence, duplicate barrel removal, exact assembly population, unchanged Circuit JSON and supplier mismatches.
- Netlist and placement: 0 errors, 0 warnings; schematic-placement passes.
- Native routed build and separately rendered export: 0 error records, 40 metadata warnings.
- Exported artifact's independent shorts, physical geometry and silkscreen-text checks: pass.
- Native build, exported artifact and the saved zero-DRC route have byte-for-byte identical trace/via/pad/hole records.
- 166 traces, 119 via records representing 117 unique physical barrel locations; minimum drill/pad remains 0.30/0.45 mm.
- Actual plated output: only `drill-L1-L4.drl` with `Plated,1,4,PTH`; **0 incorrect spans**, 117 via drills plus 4 connector slots. Both NPTH locating holes are preserved.
- BOM and PnP: **50 rows each**; C23/C24 and TP1–TP6 excluded. All fitted BOM rows have checked package descriptions and supplier IDs.

Review files: `dist/manufacturing-review-Bes0aR/`. Its unchanged `circuit.json` SHA-256 is `2eaa15b5747519a49500ab9ebd8a07c5895a8f5dd30e3a8a3ebd476450400c8d`. Logs: `dist/export-integration-*.log`. All generated review files remain ignored and unpublished.

## Remaining release blocker

All 50 placements lack explicit supplier pin-1 calibration metadata. Exported coordinates and authored rotations are preserved and regression-tested, but JLCPCB orientation/centroid and CAM review remains required. This is missing verification, not 50 known incorrect rotations. No calibration or assembler approval is invented. Each export manifest explicitly states `releasedForManufacturing: false` and lists the affected placements.

Battery/display selection, RF stackup and first-article/firmware qualification also remain as previously documented. The code and export corrections do not certify those physical requirements. The user explicitly authorized an engineering-review-only push; manufacturing sign-off remains outstanding. Pre-publication checks are recorded in `dist/export-publish-review.log` and `dist/export-publish-fabrication.log`.

---

# Historical dependency-update audit — 2026-09-05

Verified 2026-09-05. Local changes only; no commit, GitHub push or tscircuit publication. The request to publish only after clearing blockers is not satisfied.

## Updated packages

| Package | Previous | Updated |
|---|---|---|
| tscircuit | 0.0.2463 | 0.0.2464 |
| circuit-json | 0.0.479 | 0.0.485 |
| circuit-to-svg | 0.0.410 | 0.0.413 |

These were the latest npm versions returned during this audit. The lockfile preserves the umbrella package's supported dependency graph: core 0.0.1837 and CLI 0.1.2021 remain installed. No dependency overrides or patches were used. Newer standalone core 0.0.1846 was inspected separately and still emits the same conflicting via endpoint metadata; it was not forced into the project.

The test's `AnyCircuitElement` import now comes directly from the installed `circuit-json` package, matching the runtime output rather than the umbrella's older bundled type declaration. All three schematic sheets were rendered and visually reviewed with the updated SVG renderer before updating their snapshots. Component placement, copper and electrical connections were not changed.

## Verification

- Frozen-lockfile installation and TypeScript: pass.
- 25 tests, 4 snapshots: pass.
- Source netlist and placement: 0 errors, 0 warnings; schematic-placement command passes.
- Routed Circuit JSON: 0 error records, 40 metadata warnings.
- Independent shorts: 0.
- Silkscreen text-clearance check: pass.
- 166 routed traces, 119 vias; minimum drill/pad remains 0.30/0.45 mm.
- Traces, vias, pads and holes match the saved zero-DRC copper byte-for-byte.
- Fabrication gate: **fails with 69 drill-span conflicts**, unchanged.

Validated `dist/index/circuit.json` SHA-256: `36f9665f27382e90fb33c502feb9ac8598dd1d1329c2523f98cd09898fe1f91c`.

Logs are retained under ignored `dist/package-update-*.log` paths. A successful CLI build exit alone was not treated as verification.

## Actual export confirms the blockers

The native `tsci export` Gerber output was inspected, not merely inferred from metadata. It generated these non-through plated-drill files:

| Drill file | Drill coordinates |
|---|---:|
| drill-L1-L2.drl | 37 |
| drill-L1-L3.drl | 29 |
| drill-L2-L4.drl | 1 |
| drill-L3-L4.drl | 2 |
| **Total conflicting spans** | **69** |

The intended construction uses through vias only. The exporter chooses `from_layer`/`to_layer` before `layers`, while the core retains routing transition endpoints alongside full-stack physical copper layers. The canonical producer/exporter behavior must be reconciled and regression-tested; rewriting generated JSON or weakening the fabrication check is not a fix.

The same archive's BOM and pick-and-place CSVs contain all 58 component/test-pad rows, including both DNP RF capacitors and all six bare test pads. The intended fitted count is 50. BOM footprint fields are also blank. Assembly exclusion, footprint metadata and rotation review therefore remain unresolved as documented in `FABRICATION_NOTES.md`.

For investigation only, the export is quarantined locally as `dist/UNSAFE-package-update-export-audit.zip`. **Do not order or upload this archive to a fabricator.** It is ignored and has not been published.

## Remaining work before release

1. Correct the canonical via metadata/drill-export behavior and verify every intended through drill in the final files.
2. Correct and verify assembly exclusions and manufacturing metadata in the canonical export workflow.
3. Complete manufacturer CAM/assembly review and the remaining battery, display, RF and firmware qualification decisions. Physical first-article tests are separate from software checks and cannot be claimed from a dependency update.

The package update is complete locally, but this is not a blocker-free manufacturing release. Publication remains on hold.