ShiboSoftwareDev/solar-battery-charger-module

VALIDATION.md

# Validation record

Validation date: 2026-08-18

## Passed release checks

- Toolchain: project-local `tscircuit@0.0.2225`, pinned exactly
- TypeScript: `bun run typecheck` — passed
- Schematic placement: `bunx tsci check schematic-placement` — passed
- PCB placement: `bunx tsci check placement` — 0 errors, 0 warnings
- Netlist: `bunx tsci check netlist` — 0 errors, 0 warnings
- Router: built-in `preset: "default"`, no alternate router, no effort override, and no manual PCB route paths
- Routed JSON: 40 source nets, 40 routed nets, 124 `pcb_trace` records, 98 generated vias, and 0 error records
- Physical connectivity audit: every PCB port on all 40 nets belongs to its intended copper group; 0 disconnected nets
- Gerber-mode short check at 50 px/mm: no shorts detected
- Exposed-copper audit: no routed wire below 0.10 mm; six narrower autorouter pad-entry records lie completely inside endpoint pad copper
- Thermal/plated holes: 9 component PTH records (2 terminal holes, 4 BQ24650 exposed-pad vias, 3 TPS63031 exposed-pad vias), plus 98 generated 0.15/0.35 mm vias
- Outline: 66.12 × 57.00 mm with eight copper-around-semicircular-opening plated-edge contacts
- Gerber archive: 12 entries containing top/bottom copper, mask, paste, silkscreen, Edge.Cuts, fabrication drawing, plated drill, and NPTH drill
- Gerber and KiCad ZIP integrity: passed `unzip -t`
- Assembly BOM: 60 placed components, 34 grouped rows, 34 unique LCSC codes
- PnP: 60 top-side component rows; PCB-only J_CTRL/J_IO contacts omitted
- Stock-set audit: the BOM's 34 LCSC codes exactly equal the 34-code availability snapshot set
- Stock snapshot on 2026-08-17: all 34 codes reported positive inventory; the lowest-count critical line was BQ24650 C53712 at 557 units

## Release hashes

- Gerber archive SHA-256: `277a5e479ab1c9a3f56ad5625cb86213c9cebefa2bb15d7cfaf0e3862a808476`
- Routed Circuit JSON SHA-256: `94504748739a95f440a01110b103a7ac7b477640c6c987512fd7ac093eec4f6b`
- KiCad archive SHA-256: `80a9798f7ee5c61a20cae02bec2d62bebed654595f658b19c90f275a914d6a7a`
- Assembly BOM SHA-256: `c065721e416ca57bb78e2f4497b56624c04ab310f0ac60a76a839b33e538c670`
- Pick-and-place SHA-256: `6ee74e76ac4410d5a5d07ef462940a2b47cf5f9cc8be215d1a8c6ec23c6b1d2a`

## Manufacturing-rule basis

The release targets JLCPCB's published 2-layer/1 oz limits: 0.10/0.10 mm trace/space, 0.10 mm pad-to-track clearance, 0.15 mm drilling, and 0.15–0.55 mm filled/capped via-in-pad compatibility. Black solder mask's published 1 oz minimum pad spacing is 0.13 mm; the board specifies 0.15 mm different-net pad clearance. The edge contacts require JLCPCB's plated-edge process and ENIG.

Do not order this exact release with 2 oz copper: JLCPCB publishes 0.16/0.16 mm for 2-layer 2 oz boards, while this design intentionally contains 0.10 mm local clearances.

## Tool limitations handled by the release process

- `--ignore-pin-specification-drc` suppresses only missing generic-import power-pin metadata. Placement, routing, clearance, connectivity, and shorts checks are still active.
- React prints a `key is not a prop` warning while expanding keyed generated traces. It does not change the routed output.
- The pinned `@tscircuit/copper-pour-solver@0.0.42` patch makes the Si7288DP polygon power pads real cleared pour obstacles.
- Remote 3D model downloads failed during preview/KiCad generation. Models are cosmetic and do not affect footprints, copper, drills, BOM, PnP, SVG, or Gerbers.
- The optional KiCad export is for inspection/interchange. The direct Gerber export is the manufacturing source of truth.

## Release gate outside CAD

Obtain JLCPCB engineering approval for the supplied plated-edge geometry and filled/capped 0.15/0.35 mm via-in-pad before production. Build and bench-test a first article. Passing CAD and CAM checks does not prove analog control-loop stability, thermal performance, battery safety, EMC, or workmanship.